1. Field of the Invention
This invention relates to MOS devices having LDD regions with graded junctions and methods of making same.
2. Description of the Related Art
In the continuing design of VLSI devices or chips with an ever increasing number of transistors and associated circuitry formed on the same amount of space, shrinkage or sizing down of each component has created further problems which must be dealt with in the construction of the VLSI chip. The shrinkage in size of MOS transistors results in a shorter channel length and this has created problems with respect to the electric field created near the drain region which can cause short channel effects or punchthrough in which the current begins to flow in uncontrolled form through the substrate beneath the channel.
To remedy this short channel or punch through effect, it has been proposed to grade the doping or impurities in the substrate by forming a lightly doped drain region (LDD) adjacent the channel with a more heavily and deeper doped drain region, in turn, formed adjacent the LDD region. The reduced or spread out fields of the lightly doped drain structure mitigates short-channel effects, reduce hot-carrier generation, and increase the junction breakdown voltage.
The problems of lower junction breakdown voltage and hot electron injection due to the sharp impurity profile of the drain junction and the proposed remedy of forming a lightly doped drain region were first discussed by Bassous et al in an article entitled "Self-Aligned Polysilicon Gate MOSFETs with Tailored Source and Drain Profiles" which appeared in IBM Technical Disclosure Bulletin Vol. 22, No. 11, in April 1980. Bassous et al proposed thermally oxidizing a polysilicon gate and the silicon substrate followed by reactive ion etching to form an oxide sidewall on the polysilicon gate following were implanted N+ using the oxide sidewall as a shield. The oxide sidewall was then stripped followed by an N- implant to form N- or lightly doped source and drain regions in the substrate between the N+ source and drain regions and the channel beneath the gate electrode.
FIGS. 1 and 2a illustrate how such lightly doped source and drain regions (LDD regions) are typically formed in this method. Oxide spacers 14 are formed on the side of a polysilicon strip 10 which forms the gate electrode, over gate oxide 16, for several MOS transistors formed in exposed silicon portions 20 as best seen in FIG. 1. Oxide spacers 14 are formed by depositing or growing a layer of oxide (silicon dioxide) over the structure including polysilicon strip 10 and then RIE etching the structure to remove the majority of the oxide leaving only the oxide spacers 14 due to their increased thickness in the step region of the oxide layer caused by the raised polysilicon strip.
The structure may then be N+ implanted to form the N+ source and drain regions 17 shown in FIG. 2a with oxide shoulders 14 shielding the substrae region immediately adjacent the channel region to be formed under gate electrode 10. Subsequently oxide shoulders 14 are removed, thereby permitting an N- implant in the previously shielded regions of the substrate shown outlined in dotted lines at 15.
However, as shown in FIG. 2b, during the initial formation of oxide spacers 14 by RIE etching of the oxide layer, the field oxide 18 surrounding exposed silicon portions 20 may also be partially etched away as well, as shown by dotted lines 19 in field oxide layer 18, thereby giving rise to what may be severe topography problems.
Earlier, in an article entitled "A Quadruply Self-Aligned MOS (QSA MOS) A New Short Channel High Speed High Density MOSFET for VLSI" published at pp. 581-584 in IEDM in 1979, Ohta et al had proposed controlling or grading the depth of a single implant by forming a layer of oxide over a polysilicon gate electrode and then forming a nitride layer over the oxide layer which was patterned to extend laterally beyond the polysilicon gate and over a portion of the oxide layer over the substrate. The oxide layer was then reactive ion etched, using this nitride portion as a mask, resulting in horizontal portions of oxide remaining on the substrate extending laterally from the polysilicon gate electrode. A subsequent source and drain ion implant gave rise to deeper implanted regions further away from the gate electrode and more shallow implanation where the ions passed through the oxide layer resulting in shallow and deep implanted source and drain regions.
Subsequent to these publications, others have also published proposed methods of forming such lightly doped drain regions. Ogura et al, in "Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor", published in the IEEE Transactions on Electron Devices, Vol. ED-27, No. 8, in August of 1980, describe a method for forming such regions by first forming a column on a substrate comprising a polysilicon layer, a silicon nitride layer, and a silicon oxide layer. Using this column as a mask, the substrate is N+ implanted after which the polysilicon is overetched, undercutting the overlying nitride and oxide layers. The oxide and nitride layers are then removed and the substrate is then N- implanted to form N- regions in the substrate area beneath where the polysilicon was removed after the N+ implantation.
Tsang et al, in a paper entitled "Fabrication of High-Performance LDDFET's with Oxide Sidewall-Spacer Technology", published in the IEEE Transactions on Electron Devices, Vol. ED-29, No. 4, in April 1982, describe a method of forming LDD regions by first forming a polysilicon gate electrode, N- doping the substrate around the gate electrode, forming a silicon oxide layer over the structure which is then RIE etched to form oxide spacers on the sidewalls of the polysilicon gate electrode. Using these spacers as shields, the substrate is then N+ implanted. The original N- doping results in the formation of LDD regions between the channel under the gate electrode and the N+ regions source and drain subsequently implanted in the substrate.
Parillo et al, in an article entitled "A Versatile, High-Performance, Double-Level-Poly Double-Level-metal, 1.2-Micron CMOS Technology", IDEM, 1986, pp. 244-247, describe constructing MOS devices using a disposable polysilicon spacer which is formed on the sidewall of the gate electrode following which an N+ implant to form source and drain regions is performed. The polysilicon spacers are then removed and an N- implant is made resulting in N- regions in the substrate adjacent to the gate electrode and separating the N+ regions from the channel formed in the substrate beneath the gate electrode.
Numerous patents have also been granted on methods of making LDD source and drain regions for MOS devices. Simko et al U.S. Pat. No. 3,996,657 teaches the formation of a double gate MOS device wherein a gate electrode which will become a floating gate is first formed over a gate oxide on a substrate layer. The substrate is then doped with N- impurities to form lightly doped source and drain regions in the substrate adjoining the substrate region under the gate and gate oxide. Another oxide layer is then formed over and around the floating gate and a second layer of polysilicon is formed over the second oxide layer. After the deposition of the second polysilicon layer, standard photo etching techniques are utilized in order to define the primary source and drain windows. After this etching step, an ordinary diffusion step is utilized to highly dope primary source and drain regions in the substrate. Because of the oxide formed on the side of the floating gate and its retention during the etching step to form the windows, the highly doped source and drain regions in the substrate under the windows are separated from the channel under the floating gate by a distance equal to the thickness of the oxide between the floating gate and the source and drain windows. Thus, lightly doped source and drain regions are formed between the channel and the highly doped primary source and drain regions in the substrate layer.
Yau U.S. Pat. No. 3,997,367 describes a method of making a transistor with an inactive base region which is separated from an emitter region by a lightly doped buffer region. A bar of photoresist is formed over a layer of silicon nitride which is, in turn formed over a passivating layer of oxide on an epitaxial silicon layer. The structure is implanted through the nitride/oxide layers to form inactive base regions following which the reist bar is trimmed in width by plasma etching or the like. The nitride layer, formerly beneath the resist but now exposed, may be optionally removed followed by implantation of the structure at a lower dosage to form the lightly doped buffer regions. The exposed nitride, if still remaining, is then removed, as well as the remaining photoresist, and the implanted areas are then oxidized. The remaining nitride formerly beneath the remaining portion of the photoresist is then removed and the active base and emitter are formed by implantation of the region formerly covered by the nitride. The patentee states that this method can be applied to IGFET devices by using an oversize resist mask to initially form the polysilicon gate and then, after implanting the source and drain, etching the resist mask and the underlying polysilicon gate to the desired final size. This is said to compensate for the expected lateral movement of the implanted source and drain.
Shibata et al U.S. Pat. No. 4,109,371 discloses a method of making an MOS device wherein the gate electrode is formed over a gate oxide layer following which source and drain auxiliary regions are implanted using the gate electrode as a mask. An oxide layer is then formed over the gate electrode and auxiliary regions. Contact holes are formed through the oxide layer and then source and drain deep junction regions are formed by diffusing or implanting the substrate through the holes.
Roche U.S. Pat. No. 4,160,683 teaches a process for making an MOS device wherein openings for source and drain contact regions are opened through an oxide layer following which the substrate is doped by diffusion through these openings to form source and drain regions. After removal of the oxide layer, a gate oxide layer is formed with openings to the source and drain regions and a metal layer is formed over the gate oxide layer. The metal layer is patterned to form source, drain, and gate contacts with spaces therebetween over the gate oxide. The underlying substrate is implanted through these spaces to form regions between the previously formed source and drain contact regions and the channel beneath the gate electrode. In another embodiment, the regions between the source and drain contact regions and the channel are doped by diffusion from layers of doped silica formed over the structure.
Jecmen U.S. Pat. No. 4,198,250 describes a process for forming an MOS device using a shadow mask to form lightly doped sources and drain regions adjacent the channel region beneath the gate electrode. An oxide layer is formed over the polysilicon layer from which the gate electrode will be formed. The oxide layer is patterned to define a portion wider than the intended gate electrode. A wet etching step is then performed on the polysilicon layer resulting in lateral etching beneath the patterned oxide to form an oxide overhang. Ion implantation of the substrate results in the formation of the source and drain regions with lightly doped extensions adjacent the channel resulting from the partial shielding of the substrate during implantation by the oxide overhang over the gate electrode.
Komeda et al U.S. Pat. No. 4,204,894 discloses a process for forming an MOS device wherein a first oxide layer formed over a gate electrode and over adjacent portion of the substrate contains dopant with a low diffusion constant. A second oxide layer is formed over the first layer and openings are formed in the two layers where source and drain contact regions are to be formed in the substrate. A third oxide layer with a high concentration of dopant is formed over the structure and in contact with the substrate through the openings. Subsequently the structure is heated and the dopants in the oxide layers diffuse into the substrate to form shallow source and drain regions under the first oxide layer and deeper source and drain regions under the third oxide layer.
Ho et al U.S. Pat. No. 4,209,349 describes a method for making a double diffusion MOS device wherein layers of nitride and oxide over a silicon substrate are patterned to define openings the source and drain regions which are formed in the underlying substrate by diffusion of P-type ions through the openings. A second insulation layer of oxide is then applied over the structure and RIE etched to form shoulders on the side edges of the patterned nitride/oxide layers which act to narrow the lateral dimensions of the source/drain openings therein. N+ ions are then diffused through these narrowed openings to form N+ regions in the substrate which extend to a lower depth than the originally formed P regions but not as wide, leaving P regions in the substrate. Source and drain contacts are then formed to the N+ regions and a gate electrode, including gate oxide, is formed over over the region of the substrate between the p regions adjacent the N+ source/drain regions.
Ho et al U.S. Pat. No. 4,209,350 teaches a method for making an MOS structure in which a silicon dioxide layer on a silicon substrate is patterned to form openings where it is desired to have source and drain regions formed in the substrate. A second layer of oxide, heavily doped with P+, is formed over the patterned first oxide layer and then RIE etched leaving shoulders or side pieces on the sidewalls of the originally formed source and drain openings in the first oxide layer. The substrate is then doped by implanting or diffusing N+ ions through the source and drain openings. During the drive-in for the ion implantation or diffusion, the P+ dopant from the second oxide layer diffuses into the substrate to form very narrow P effective channel regions in the substrate which are not as deep as the adjacent N+ source and drain regions. Gate, source, and drain electrodes are then conventionally formed.
Riseman U.S. Pat. No. 4,234,362 discloses methods for making transistor structures including MOS structures wherein a conformal insulator layer is applied over a polysilicon gate electrode and the RIE etched to form an insulating sidewall on the gate electrode. This insulating sidewall, together with an oxide layer formed over the gate electrode, electrically separates the gate electrode from a subsequently applied polysilicon layer used to form one electrode of a capacitor. The patent also illustrates the use of a conformal insulating layer to form vertical sidewalls on polysilicon strips between which openings are formed to dope the underlying substrate to form emitter and collector reach-through regions therein.
Pogge U.S. Pat. No. 4,256,514 describes a method of making a narrow dimension region on a silicon body wherein regions are formed on the silicon body having substantially horizontal surfaces and substantially vertical surfaces, i.e., a groove formed in the silicon body. A layer is then formed over this structure and the horizontal portions removed by reactive ion etching leaving only the vertical portions, i.e., on the sidewalls of the groove, defining a narrow opening to the substrate through which the substrate may be doped.
Hunter et al U.S. Pat. No. 4,354,896 teaches the formation of a submicron line width wherein a top layer of nitride is patterned and then an underlying oxide layer is etched to undercut the nitride layer. A conformal layer of polysilicon is applied which fills in the undercut portion. A dry isotropic etch is used to remove the conformal layer except for the portion filling in the undercut. The overlying nitride layer is then removed as is the remainder of the oxide layer leaving only the undercut portion of the polysilicon layer which is then used as a mask to etch underlying layers.
Hunter U.S. Pat. No. 4,356,623 discloses a method for fabricating an MOS structure wherein a gate electrode is first formed and then, either before or after an initial doping of the substrate to form source and drain regions, a conformal layer is applied and etched to form shoulders on the side of the gate electrode. Subsequent doping of the substrate at a higher energy than the first implantation forms source and drain regions adjacent the initially formed regions. The first source and drain regions are, however, masked by the conformal layer shoulders so the second implantation forms deeper regions adjoining the initially formed shallow regions. In another embodiment, the shoulder are formed prior to the first implantation and a second set of shoulders are then formed after the first implantation but prior to a second implantation.
Ogura et al U.S. Pat. No. 4,366,613 describes the formation of an MOS device wherein a gate electrode is formed over a substrate, N- source and drain regions are implanted in the substrate adjacent the electrode, an insulator layer is formed over the gate electrode and the substrate, the insulator layer is reactive ion etched to form sidewall spacers on the sides of the gate electrode, and then the substrate is N+ implanted to form N+ source and drain regions adjacent the N- regions with the N- regions separating the N+ source and drain regions from the channel formed in the substrate beneath the gate electrode.
In my prior patent, Haskell U.S. Pat. No. 4,516,316, I describe the formation of separate doped regions in a substrate by forming a first oxide layer over a substrate, a phosphorus doped polysilicon layer over the first oxide layer, a second oxide layer over the polysilicon layer, and a nitride layer. The three upper layers are patterned to expose a portion of the first oxide layer. The substrate is then doped by implantation through the first oxide layer. The three upper layers mask the remainder of the substrate. An oxide layer is then grown over the first oxide layer and the implanted substrate as well as the exposed sidewall of the polysilicon layer by steam oxidation which preferentially oxidizes the polysilicon sidewall rather than the silicon substrate due to the phosphorus dopant therein. This preferential lateral oxidation of the polysilicon sidewall undercuts the overlying oxide and nitride layers giving a large offset. The nitride, second oxide, and polysilicon layers are then removed and the substrate is again implanted with the oxide grown over the previously implanted substrate shielding it from the second implantation. In addition, the undercutting of the nitride layer by the oxide grown into the sidewall of the polysilicon layer results in a gap in the substrate between the two implanted regions. Subsequent annealing of the implanted regions causes the two doped regions to spread toward one another and optionally to touch one another.
Although many ways have thus been proposed to solve the short channel and punchthrough problem, including many ways of forming the lightly doped drain region, the use of oxide spacers has been the most widely used approach. However, as shown by comparing FIG. 2a with FIG. 2b, while the RIE etching of the oxide layer may use the underlying silicon 20 as an etch stop or end point for the etch, as in FIG. 2a, in the field oxide region between adjacent MOS devices, as shown in FIG. 2b, there is no silicon at the surface of the structure and the RIE etching will etch away grooves 19 in field oxide 18 which, if not filled, can adversely affect the topography, and, if filled, can result in the formation of voids in the filler material which can subsequently result in reliability problems from inclusion of contaminants. Also if the voids are exposed, they may etch preferentially or oxidize which can, in turn, stress the substrate.
To avoid the problem of over etching into the field oxide between adjacent devices, it has been proposed, as discussed above, for example, with regard to the Parillo et al article, to replace the prior art oxide spacers or shoulders shown in FIGS. 1 and 2a-2b with polysilicon spacers which would be formed by RIE etching a conformal polysilicon layer which would be formed over the structure (after first forming a thin oxide layer which would serve to separate the polysilicon gate strip from the conformal polysilicon layer). However, the use of a conductive material such as polysilicon to form the spacers adjacent the gate electrode necessitates the subsequent removal of such polysilicon spacers since they would be electrically floating and could cause threshold shifts.
Stripping the polysilicon spacers from the structure would, in itself, cause further problems if the quality of the oxide separating the polysilicon spacer from the polysilicon gate was not perfect since the etchant used to remove the polysilicon spacer might penetrate the oxide to attack the polysilicon gate. In addition, if there are pinholes in the oxide layer, which is formed over the polysilicon gate prior to deposition of the conformal layer of polysilicon used to form the polysilicon spacers, the two polysilicon layers may coalesce and the subsequent RIE etching to form the spacer will etch through these areas instead of stopping on the oxide layer.
Thus, there remains a need for solving the problem of short channel effects such as punchthrough in MOS transistors used in VLSI structures by constructing lightly doped drain regions without incurring the additional problems of the prior art which can occur when either oxide or polysilicon spacers are used in the course of the formation of lightly doped source and drain regions.